Emitter-coupled logic (ECL) is a desired technology for logic circuitry because its provides very fast switching times. Computers and other logic devices requiring very fast operation have been implemented using ECL.
Besides the high-speed switching available with ECL, the technology provides the further advantage of presenting to the designer a circuit which provides, for example, a logic OR output and a complementary logic NOR output. Thus the flexibility of designing with ECL is greater than other logic circuit technologies which do not provide the complementary outputs. Of course, ECL may likewise be configured to perform other logic functions as is known in the art.
Conventionally, the output voltage of an ECL circuit has been driven with an emitter follower transistor. The emitter follower transistor provides a low-impedance output which actively provides current to drive the output voltage from a low value to a high value. However, when the ECL output is to switch from a high value to a low value, the emitter follower output transistor would not provide a source to pull the output voltage down. Rather the voltage was left to passively drop.
If the output voltage of the ECL circuit drives a capacitive load, the switching time of the output during the swing from a high voltage to a low voltage would increase due to the capacitive load without an active pull-down current. Thus a capacitive load would substantially slow down the ECL output.
One way to improve the switching time from the high voltage to the low voltage for the ECL output driving a capacitive load, in the prior art, has been to provide a steady-state current source to pull a constant current through the emitter follower, or a resistor allowing current to flow during steady state through the emitter follower, in order to provide a pull-down current for the capacitive load. However, it is found that as the capacitance of the load increases, the amount of steady-state pull-down current required to obtain acceptable switching speeds has been large. With the high steady-state pull-down current increasing in size to increase the speed of the circuit, the power consumed by the circuit would increase unfavorably.
With the advent of integrated circuit technology and the ever-increasing number of devices on a given chip, the load capacitance of ECL gates on the chip has likewise increased. This load capacitance is due in part to the ever-lengthening amount of leads formed on the chip in order to connect a number of devices to a given output, and to the fact that a given output is required to drive a large number of devices, each having an inherent capacitance. This increased number of devices being driven by an ECL circuit can be termed as an increasing fan-out of the output voltage of the particular ECL circuit. Thus, as the fan-out of an ECL circuit increases, so does the load capacitance.
A good discussion of the fundamentals of ECL circuitry can been found in the book, Analysis and Design of Digital Integrated Circuits, by David A. Hodges and Horace G. Jackson (McGraw-Hill Book Co., 1983), pages 271-283.
With the increase in load capacitance being driven by ECL circuits, the output driver circuit of the prior art consisting of an emitter follower transistor with a DC pull-down current has proven to be a limiting factor in the speed and steady state power dissipation of logic circuits using ECL. Thus there is a need for an output voltage driver circuit which provides for a faster switching time with a given steady state power dissipation for ECL circuits driving a capacitive load.